Consider the FSM described by the state diagram shown below:
This FSM acts as an arbiter circuit, which controls access to some type of resource by three requesting devices. Each device makes its request for the resource by setting a signalr[i]= 1, wherer[i]is eitherr[1],r[2], orr[3]. Each r[i] is an input signal to the FSM, and represents one of the three devices. The FSM stays in stateAas long as there are no requests. When one or more request occurs, then the FSM decides which device receives a grant to use the resource and changes to a state that sets t服务器托管网hat device’sg[i]signal to 1. Eachg[i]is an output from the FSM. There is a priority system, in that device 1 has a higher priority than device 2, and device 3 has the lowest priority. Hence, for example, device 3 will only receive a grant if it is the only device making a request when the FSM is in stateA. Once a device,i, is given a grant by the FSM, that device continues to receive the grant as long as its request,r[i]= 1.
Write complete Verilog code that represents this FSM. Use separate always blocks for the state table and t服务器托管网he state flip-flops, as done in lectures. Describe the FSM outputs,g[i], using either continuous assignment statement(s) or an always block (at your discretion). Assign any state codes that you wish to use.
module top_module (
input clk,
input resetn, // active-low synchronous reset
input [3:1] r, // request
output [3:1] g // grant
);
parameter free=0,e1=1,e2=2,e3=3;
reg [1:0] state,next;
always@(*) begin
case(state)
free:begin
if(r==3'b000)
next服务器托管，北京服务器托管，服务器租用 http://www.fwqtg.net
注意： 1、每一个case后面要有break 2、/运算的时候注意分母不能为0 int a, b; char c; cin>服务器托管网;>a>>b>>服务器托管网;c; switch (c) { case ‘+…
