0. 环境
– ubuntu18
– vivado 2018.3
– mizar z7010 + ada106模块
1. vivado
1.1 创建vivado工程
运行vivado
source /tools/Xilinx/Vivado/2018.3/settings64.sh
vivado&创建vivado工程
Vivado -> Create Project -> Next ->
-> Project name: linux_sd_adda
-> project location: /home/xxjianvm/work/mizar/
-> Next
-> RTL Project -> Next
-> Next
-> Next
-> Default part: xc7z010CLG400-1 -> Next
-> Finish
-> Finish
1.2 建立IP- PS_PL_DAC_8B
130个32位的寄存器定义
序号 定义
0 控制1，PS写，采样频率设置
1 控制2，PS写，高16位是DAC使能，低16位是数据长度
2 回复1，PL写，
3-129 数据，PS写
1.2.1 添加IP
Tools -> Create and Package New IP -> Next
-> Create a new AXI4 peripheral -> Next
-> Name: PS_PL_DAC_8B
-> Description: PS_READ_WRITE_PL_REG for dac 8 bit
-> IP location: /home/xxjianvm/work/mizar/ip_repo
-> Next
-> Add Interface
-> Number of Registers: 130
-> Next
-> Create Peripheral
-> Edit IP -> Finish
1.2.2编辑IP
1.2.2.1 基本端口定义
双击 PS_PL_DAC_8B_v1_0.v
修改第 17 行
// Users to add ports here
input wire clk_50m,
output wire dac_clk,
output wire [7:0] dac_data,
output wire dac_pd,
// User ports ends
修改第 76 行：
.clk_50m ( clk_50m ),
.dac_clk ( dac_clk ),
.dac_data ( dac_data),
.dac_pd ( dac_pd )
1.2.2.2 双击 PS_PL_DAC_8B_v1_0_S00_AXI_inst
修改端口，第17行：
// Users to add ports here
input wire clk_50m,
output wire dac_clk,
output reg [7:0] dac_data,
output wire dac_pd,
// User ports ends slv_reg2改为PL写。注释掉alway模块内的这几行，slv_reg2就改为PS只读不可写。
注释：
// slv_reg2 注释
// slv_reg2[(byte_index*8) +: 8] 注释
// slv_reg2 
1.2.2.3 时钟信号
-> Project Manager -> IP Catalog -> clocking wizard ->
-> Component Name: clock
-> Clocking Options
-> Input Clock Information
-> Primary frequency: 50Mhz
-> Output Clocks
-> clk_out1: 128MHz
-> Enable Optional Inputs / Outputs for MMCM/PLL:
-> 取消勾选lcoked
-> Reset Type: Active Low
-> OK -> Generate
1.2.3编写verilog文件，根据寄存器0，设置时钟
创建文件 da9708_clkswitch.v
这里寄存器0的定义是设置DAC采样频率。为了简便，这个DAC只支持几个64倍数的采样频率。
module da9708_clkswitch
(
clk_128m,
rst_n,
slv_reg0,
clk_64m,
clk_25p6m,
clk_12p8m,
clk_6400k,
clk_2560k,
clk_1280k,
clk_640k,
clk_256k,
clk_128k,
clk_64k,
clk_25600,
clk_12800,
clk_6400,
clk_2560,
clk_1280,
clk_640,
clk_256,
clk_128,
clk_64,
clk_25p6,
clk_12p8,
clk_6p4,
clk_dac
);
input wire clk_128m;
input wire rst_n;
input wire [31:0] slv_reg0;
input wire clk_64m;
input wire clk_25p6m;
input wire clk_12p8m;
input wire clk_6400k;
input wire clk_2560k;
input wire clk_1280k;
input wire clk_640k;
input wire clk_256k;
input wire clk_128k;
input wire clk_64k;
input wire clk_25600;
input wire clk_12800;
input wire clk_6400;
input wire clk_2560;
input wire clk_1280;
input wire clk_640;
input wire clk_256;
input wire clk_128;
input wire clk_64;
input wire clk_25p6; // 低速时钟用来判断按键
input wire clk_12p8;
input wire clk_6p4;
output reg clk_dac;
//
always @( posedge clk_128m or negedge rst_n) begin
if( ~rst_n ) begin
clk_dac = 32'd64_000_000 ) begin
clk_dac = 32'd25_600_000 ) begin
clk_dac = 32'd12_800_000 ) begin
clk_dac = 32'd6_400_000 ) begin
clk_dac = 32'd2_560_000 ) begin
clk_dac = 32'd1_280_000 ) begin
clk_dac = 32'd640_000 ) begin
clk_dac = 32'd256_000 ) begin
clk_dac = 32'd128_000 ) begin
clk_dac = 32'd64_000 ) begin
clk_dac = 32'd25_600 ) begin
clk_dac = 32'd12_800 ) begin
clk_dac = 32'd6400 ) begin
clk_dac = 32'd2560 ) begin
clk_dac = 32'd1280 ) begin
clk_dac = 32'd640 ) begin
clk_dac = 32'd256 ) begin
clk_dac = 32'd128 ) begin
clk_dac = 32'd64 ) begin
clk_dac = 32'd25 ) begin
clk_dac = 32'd12 ) begin
clk_dac = 32'd6 ) begin
clk_dac 1.2.4 编写verilog，对128M时钟分频
1.2.4.1 da9708_clkevery.v
module da9708_clkevery
(
clk_128m,
rst_n,
clk_64m,
clk_25p6m,
clk_12p8m,
clk_6400k,
clk_2560k,
clk_1280k,
clk_640k,
clk_256k,
clk_128k,
clk_64k,
clk_25600,
clk_12800,
clk_6400,
clk_2560,
clk_1280,
clk_640,
clk_256,
clk_128,
clk_64,
clk_25p6,
clk_12p8,
clk_6p4
);
input clk_128m;
input rst_n;
output clk_64m;
output clk_25p6m;
output clk_12p8m;
output clk_6400k;
output clk_2560k;
output clk_1280k;
output clk_640k;
output clk_256k;
output clk_128k;
output clk_64k;
output clk_25600;
output clk_12800;
output clk_6400;
output clk_2560;
output clk_1280;
output clk_640;
output clk_256;
output clk_128;
output clk_64;
output clk_25p6;
output clk_12p8;
output clk_6p4;
// 时钟生成模块 64m
clk_div10 clk_div10_inst_0(
.clk( clk_128m ),
.rstn( rst_n ) ,
.clk_div2( clk_64m )
);
// 时钟生成模块 25.6m, 12.8m, 6400k
clk_div2p5 clk_div2p5_inst_1(
.clk( clk_64m ),
.rstn( rst_n ) ,
.clk_div2p5( clk_25p6m )
);
clk_div5 clk_div5_inst_1(
.clk( clk_64m ),
.rstn( rst_n ) ,
.clk_div5( clk_12p8m )
);
clk_div10 clk_div10_inst_1(
.clk( clk_64m ),
.rstn( rst_n ) ,
.clk_div10( clk_6400k )
);
// 时钟生成模块 2560k, 1280k, 640k
clk_div2p5 clk_div2p5_inst_2(
.clk( clk_6400k ),
.rstn( rst_n ) ,
.clk_div2p5( clk_2560k )
);
clk_div5 clk_div5_inst_2(
.clk( clk_6400k ),
.rstn( rst_n ) ,
.clk_div5( clk_1280k )
);
clk_div10 clk_div10_inst_2(
.clk( clk_6400k ),
.rstn( rst_n ) ,
.clk_div10( clk_640k )
);
// 时钟生成模块 256k, 128k, 64k
clk_div2p5 clk_div2p5_inst_3(
.clk( clk_640k ),
.rstn( rst_n ) ,
.clk_div2p5( clk_256k )
);
clk_div5 clk_div5_inst_3(
.clk( clk_640k ),
.rstn( rst_n ) ,
.clk_div5( clk_128k )
);
clk_div10 clk_div10_inst_3(
.clk( clk_640k ),
.rstn( rst_n ) ,
.clk_div10( clk_64k )
);
// 时钟生成模块 25600, 12800, 6400
clk_div2p5 clk_div2p5_inst_4(
.clk( clk_64k ),
.rstn( rst_n ) ,
.clk_div2p5( clk_25600 )
);
clk_div5 clk_div5_inst_4(
.clk( clk_64k ),
.rstn( rst_n ) ,
.clk_div5( clk_12800 )
);
clk_div10 clk_div10_inst_4(
.clk( clk_64k ),
.rstn( rst_n ) ,
.clk_div10( clk_6400 )
);
// 时钟生成模块 2560, 1280, 640
clk_div2p5 clk_div2p5_inst_5(
.clk( clk_6400 ),
.rstn( rst_n ) ,
.clk_div2p5( clk_2560 )
);
clk_div5 clk_div5_inst_5(
.clk( clk_6400 ),
.rstn( rst_n ) ,
.clk_div5( clk_1280 )
);
clk_div10 clk_div10_inst_5(
.clk( clk_6400 ),
.rstn( rst_n ) ,
.clk_div10( clk_640 )
);
// 时钟生成模块 256, 128, 64
clk_div2p5 clk_div2p5_inst_6(
.clk( clk_640 ),
.rstn( rst_n ) ,
.clk_div2p5( clk_256 )
);
clk_div5 clk_div5_inst_6(
.clk( clk_640 ),
.rstn( rst_n ) ,
.clk_div5( clk_128 )
);
clk_div10 clk_div10_inst_6(
.clk( clk_640 ),
.rstn( rst_n ) ,
.clk_div10( clk_64 )
);
// 时钟生成模块 25.6, 12.8, 6.4
clk_div2p5 clk_div2p5_inst_7(
.clk( clk_64 ),
.rstn( rst_n ) ,
.clk_div2p5( clk_25p6 )
);
clk_div5 clk_div5_inst_7(
.clk( clk_64 ),
.rstn( rst_n ) ,
.clk_div5( clk_12p8 )
);
clk_div10 clk_div10_inst_7(
.clk( clk_64 ),
.rstn( rst_n ) ,
.clk_div10( clk_6p4 )
);
endmodule
1.2.4.2 clk_div10.v
网上下载的时钟10分频：
module clk_div10
# (parameter DIV_CLK = 10 )
(
input rstn ,
input clk,
output clk_div2,
output clk_div4,
output clk_div10
);
//2 分频
reg clk_div2_r ;
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
clk_div2_r 1.2.4.3 clk_div5.v
时钟5分频是网上下载的。
module clk_div5
#(parameter DIV_CLK = 5)
(
input rstn ,
input clk,
output clk_div5
);
//计数器
reg [3:0] cnt ;
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
cnt >1)-1 ) begin //计数4-8位低电平
clkp_div5_r >1)-1 ) begin
clkn_div5_r 1.2.4.4 clk_div2p5.v
时钟 2.5分频
module clk_div2p5(
input clk,
input rstn ,
output clk_div2p5
);
//计数器
parameter MUL2_DIV_CLK = 5 ;
reg [3:0] cnt ;
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
cnt 1.2.5 编写dac_clk驱动
dac_clk_sw.v
封装 da9708_clkswitch.v 和 da9708_clkevery.v， 实现根据寄存器0输出dac_clk，dac_clk_sw.v
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 02/18/2024 11:40:35 AM
// Design Name:
// Module Name: dac_clk_sw
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module dac_clk_sw(
clk_128m,
rst_n,
slv_reg0,
clk_dac
);
input wire clk_128m;
input wire rst_n;
input wire [31:0] slv_reg0;
output wire clk_dac;
// 按键选择模块
da9708_clkswitch da9708_clkswitch_inst (
.clk_128m ( clk_128m ),
.rst_n ( rst_n ),
.slv_reg0 ( slv_reg0 ),
.clk_64m ( clk_64m ),
.clk_25p6m ( clk_25p6m ),
.clk_12p8m ( clk_12p8m ),
.clk_6400k ( clk_6400k ),
.clk_2560k ( clk_2560k ),
.clk_1280k ( clk_1280k ),
.clk_640k ( clk_640k ),
.clk_256k ( clk_256k ),
.clk_128k ( clk_128k ),
.clk_64k ( clk_64k ),
.clk_25600 ( clk_25600 ),
.clk_12800 ( clk_12800 ),
.clk_6400 ( clk_6400 ),
.clk_2560 ( clk_2560 ),
.clk_1280 ( clk_1280 ),
.clk_640 ( clk_640 ),
.clk_256 ( clk_256 ),
.clk_128 ( clk_128 ),
.clk_64 ( clk_64 ),
.clk_25p6 ( clk_25p6 ),
.clk_12p8 ( clk_12p8 ),
.clk_6p4 ( clk_6p4 ),
.clk_dac ( clk_dac )
);
// 时钟生成模块
da9708_clkevery da9708_clkevery_inst1(
.clk_128m ( clk_128m ),
.rst_n ( rst_n ),
.clk_64m ( clk_64m ),
.clk_25p6m ( clk_25p6m ),
.clk_12p8m ( clk_12p8m ),
.clk_6400k ( clk_6400k ),
.clk_2560k ( clk_2560k ),
.clk_1280k ( clk_1280k ),
.clk_640k ( clk_640k ),
.clk_256k ( clk_256k ),
.clk_128k ( clk_128k ),
.clk_64k ( clk_64k ),
.clk_25600 ( clk_25600 ),
.clk_12800 ( clk_12800 ),
.clk_6400 ( clk_6400 ),
.clk_2560 ( clk_2560 ),
.clk_1280 ( clk_1280 ),
.clk_640 ( clk_640 ),
.clk_256 ( clk_256 ),
.clk_128 ( clk_128 ),
.clk_64 ( clk_64 ),
.clk_25p6 ( clk_25p6 ),
.clk_12p8 ( clk_12p8 ),
.clk_6p4 ( clk_6p4 )
);
endmodule
1.2.6 继续修改 PS_PL_DAC_8B_v1_0_S00_AXI_inst
// Add user logic here
clk_wiz_0 inst_clk_wiz_0(
.clk_in1 (clk_50m ), // input clk_in1
.resetn (S_AXI_ARESETN ), // input reset
.clk_out1 (clk_128m) // output clk_out1
);
dac_clk_sw dac_clk_sw_inst(
.clk_128m ( clk_128m ),
.rst_n ( S_AXI_ARESETN ),
.slv_reg0 ( slv_reg0 ),
.clk_dac ( dac_clk )
);
reg [15:0] dac_cnt = 16'd0;
always @( posedge dac_clk or negedge S_AXI_ARESETN ) begin
if ( S_AXI_ARESETN == 1'b0 ) begin
dac_cnt = slv_reg1[15:0] - 1'b1 ) begin
dac_cnt
1.2.7打包
PROJECT MANAGER -> Edit Package IP – PS_PL_DAC_8B ->
-> File Groups -> Merge changes from File Groups Wizard
-> Customization Parameters -> Merge changes from File Groups Wizard
-> Review and Package -> Re-Package IP
1.3 建立IP- PS_PL_ADC_8B
130个32位的寄存器定义
序号 定义
0 控制1，PS写，采样频率设置
1 控制2，PS写，高16位是采样状态控制，低16位是采样数量
2 回复1，PL写，
3-129 数据，PL写
本程序ADC采样是这样的交互过程：
PS：设置控制2为0001xxxx，空闲
PL：设置回复1为0001xxxx，空闲
PS：设置控制2为0002xxxx，开始采样
PL：设置回复1为0002xxxx，开始采样
PL：设置回复1为0004xxxx，采样完毕
PS：设置控制2为0004xxxx，采样完毕
1.3.1 添加IP
Tools -> Create and Package New IP -> Next
-> Create a new AXI4 peripheral -> Next
-> Name: PS_PL_ADC_8B
-> Description: PS_READ_WRITE_PL_REG for adc 8 bit
-> IP location: /home/xxjianvm/work/mizar/ip_repo
-> Next
-> Add Interface
-> Number of Registers: 130
-> Next
-> Create Peripheral
-> Edit IP -> Finish
1.3.2 编辑模块端口 PS_PL_ADC_8B_v1_0.v
修改第 17 行
// Users to add ports here
input wire clk_50m,
output wire adc_clk,
input wire [7:0] adc_data,
output wire adc_pd,
// User ports ends
修改第 76 行：
.clk_50m ( clk_50m ),
.adc_clk ( adc_clk ),
.adc_data ( adc_data),
.adc_pd ( adc_pd )
1.3.3 编辑PS_PL_ADC_8B_v1_0_S00_AXI_inst
修改端口，第17行：
// Users to add ports here
input wire clk_50m,
output wire adc_clk,
input wire [7:0] adc_data,
output wire adc_pd,
// User ports ends把slv_reg2 – slv_reg511改为PL写。
把图示的always模块内的slv_reg2 – slv_reg129 都注释掉，变成PL读写，PS只读。
注释：
// slv_reg2 注释
// slv_reg2[(byte_index*8) +: 8] 注释
// slv_reg2 注意 slv_reg2 – slv_reg129 都要注释。
1.3.3 编写clk_div.v
对 50MHz的时钟分频
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 02/18/2024 02:04:13 PM
// Design Name:
// Module Name: clk_div
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module clk_div(
clk_50m,
rst_n,
clk_20m,
clk_10m,
clk_8m,
clk_5m,
clk_4m,
clk_2m,
clk_1m,
clk_800k,
clk_400k,
clk_200k,
clk_100k,
clk_80k,
clk_40k,
clk_20k,
clk_10k,
clk_8k,
clk_4k,
clk_2k,
clk_1k,
clk_800,
clk_400,
clk_200,
clk_100
);
input wire clk_50m;
input wire rst_n;
output wire clk_20m;
output wire clk_10m;
output wire clk_8m;
output wire clk_5m;
output wire clk_4m;
output wire clk_2m;
output wire clk_1m;
output wire clk_800k;
output wire clk_400k;
output wire clk_200k;
output wire clk_100k;
output wire clk_80k;
output wire clk_40k;
output wire clk_20k;
output wire clk_10k;
output wire clk_8k;
output wire clk_4k;
output wire clk_2k;
output wire clk_1k;
output wire clk_800;
output wire clk_400;
output wire clk_200;
output wire clk_100;
// 时钟生成模块 20m, 10m, 5m
clk_div2p5 clk_gen_20m(
.clk ( clk_50m ),
.rstn ( rst_n ) ,
.clk_div2p5( clk_20m )
);
clk_div5 clk_gen_10m(
.clk ( clk_50m ),
.rstn ( rst_n ) ,
.clk_div5 ( clk_10m )
);
clk_div10 clk_gen_5m(
.clk ( clk_50m ),
.rstn ( rst_n ) ,
.clk_div10 ( clk_5m )
);
// 时钟生成模块 8m, 4m, 2m
clk_div2p5 clk_gen_8m(
.clk ( clk_20m ),
.rstn ( rst_n ) ,
.clk_div2p5( clk_8m )
);
clk_div5 clk_gen_4m(
.clk ( clk_20m ),
.rstn ( rst_n ) ,
.clk_div5 ( clk_4m )
);
clk_div10 clk_gen_2m(
.clk ( clk_20m ),
.rstn ( rst_n ) ,
.clk_div10 ( clk_2m )
);
// 时钟生成模块 1m
clk_div10 clk_gen_1m(
.clk ( clk_10m ),
.rstn ( rst_n ) ,
.clk_div10 ( clk_1m )
);
// 时钟生成模块 800k
clk_div2p5 clk_gen_800k(
.clk ( clk_2m ),
.rstn ( rst_n ) ,
.clk_div2p5( clk_800k )
);
// 时钟生成模块 400k, 200k, 100k
clk_div2p5 clk_gen_400k(
.clk ( clk_1m ),
.rstn ( rst_n ) ,
.clk_div2p5( clk_400k )
);
clk_div5 clk_gen_200k(
.clk ( clk_1m ),
.rstn ( rst_n ) ,
.clk_div5 ( clk_200k )
);
clk_div10 clk_gen_100k(
.clk ( clk_1m ),
.rstn ( rst_n ) ,
.clk_div10 ( clk_100k )
);
// 时钟生成模块 80k
clk_div2p5 clk_gen_80k(
.clk ( clk_200k ),
.rstn ( rst_n ) ,
.clk_div2p5( clk_80k )
);
// 时钟生成模块 40k, 20k, 10k
clk_div2p5 clk_gen_40k(
.clk ( clk_100k ),
.rstn ( rst_n ) ,
.clk_div2p5( clk_40k )
);
clk_div5 clk_gen_20k(
.clk ( clk_100k ),
.rstn ( rst_n ) ,
.clk_div5 ( clk_20k )
);
clk_div10 clk_gen_10k(
.clk ( clk_100k ),
.rstn ( rst_n ) ,
.clk_div10 ( clk_10k )
);
// 时钟生成模块 8k, 4k, 2k, 1k
clk_div2p5 clk_gen_8k(
.clk ( clk_20k ),
.rstn ( rst_n ) ,
.clk_div2p5( clk_8k )
);
clk_div2p5 clk_gen_4k(
.clk ( clk_10k ),
.rstn ( rst_n ) ,
.clk_div2p5( clk_4k )
);
clk_div5 clk_gen_2k(
.clk ( clk_10k ),
.rstn ( rst_n ) ,
.clk_div5 ( clk_2k )
);
clk_div10 clk_gen_1k(
.clk ( clk_10k ),
.rstn ( rst_n ) ,
.clk_div10 ( clk_1k )
);
// 时钟生成模块 800, 400, 200, 100
clk_div2p5 clk_gen_800(
.clk ( clk_2k ),
.rstn ( rst_n ) ,
.clk_div2p5( clk_800 )
);
clk_div2p5 clk_gen_400(
.clk ( clk_1k ),
.rstn ( rst_n ) ,
.clk_div2p5( clk_400 )
);
clk_div5 clk_gen_200(
.clk ( clk_1k ),
.rstn ( rst_n ) ,
.clk_div5 ( clk_200 )
);
clk_div10 clk_gen_100(
.clk ( clk_1k ),
.rstn ( rst_n ) ,
.clk_div10 ( clk_100 )
);
endmodule
1.3.4 编写 adc_clk_drv.v
根据 寄存器0 slv_reg0，设置ADC时钟
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 02/18/2024 02:31:22 PM
// Design Name:
// Module Name: adc_clk
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module adc_clk(
clk_50m,
rst_n,
slv_reg0,
adc_clk
);
input wire clk_50m;
input wire rst_n;
input wire [31:0] slv_reg0;
output wire adc_clk;
reg adc_clk_r;
wire clk_20m;
wire clk_10m;
wire clk_8m;
wire clk_5m;
wire clk_4m;
wire clk_2m;
wire clk_1m;
wire clk_800k;
wire clk_400k;
wire clk_200k;
wire clk_100k;
wire clk_80k;
wire clk_40k;
wire clk_20k;
wire clk_10k;
wire clk_8k;
wire clk_4k;
wire clk_2k;
wire clk_1k;
wire clk_800;
wire clk_400;
wire clk_200;
wire clk_100;
clk_div clk_gen(
.clk_50m ( clk_50m ),
.rst_n ( rst_n ),
.clk_20m ( clk_20m ),
.clk_10m ( clk_10m ),
.clk_8m ( clk_8m ),
.clk_5m ( clk_5m ),
.clk_4m ( clk_4m ),
.clk_2m ( clk_2m ),
.clk_1m ( clk_1m ),
.clk_800k ( clk_800k),
.clk_400k ( clk_400k),
.clk_200k ( clk_200k),
.clk_100k ( clk_100k),
.clk_80k ( clk_80k ),
.clk_40k ( clk_40k ),
.clk_20k ( clk_20k ),
.clk_10k ( clk_10k ),
.clk_8k ( clk_8k ),
.clk_4k ( clk_4k ),
.clk_2k ( clk_2k ),
.clk_1k ( clk_1k ),
.clk_800 ( clk_800 ),
.clk_400 ( clk_400 ),
.clk_200 ( clk_200 ),
.clk_100 ( clk_100 )
);
always @( posedge clk_50m or negedge rst_n ) begin
if( ~rst_n ) begin
adc_clk_r = 32'd20_000_000 ) begin
adc_clk_r = 32'd10_000_000 ) begin
adc_clk_r = 32'd8_000_000 ) begin
adc_clk_r = 32'd5_000_000 ) begin
adc_clk_r = 32'd4_000_000 ) begin
adc_clk_r = 32'd2_000_000 ) begin
adc_clk_r = 32'd1_000_000 ) begin
adc_clk_r = 32'd800_000 ) begin
adc_clk_r = 32'd400_000 ) begin
adc_clk_r = 32'd200_000 ) begin
adc_clk_r = 32'd100_000 ) begin
adc_clk_r = 32'd80_000 ) begin
adc_clk_r = 32'd40_000 ) begin
adc_clk_r = 32'd20_000 ) begin
adc_clk_r = 32'd10_000 ) begin
adc_clk_r = 32'd8_000 ) begin
adc_clk_r = 32'd4_000 ) begin
adc_clk_r = 32'd2_000 ) begin
adc_clk_r = 32'd1_000 ) begin
adc_clk_r = 32'd800 ) begin
adc_clk_r = 32'd400 ) begin
adc_clk_r = 32'd200 ) begin
adc_clk_r = 32'd100 ) begin
adc_clk_r 1.3.5 编辑 PS_PL_ADC_8B_v1_0_S00_AXI.v
实现ADC控制的相关逻辑。这里直接放出源码。
`timescale 1 ns / 1 ps
module PS_PL_ADC_8B_v1_0_S00_AXI #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Width of S_AXI data bus
parameter integer C_S_AXI_DATA_WIDTH = 32,
// Width of S_AXI address bus
parameter integer C_S_AXI_ADDR_WIDTH = 10
)
(
// Users to add ports here
input wire clk_50m,
output wire adc_clk,
input wire [7:0] adc_data,
output wire adc_pd,
// User ports ends
// Do not modify the ports beyond this line
// Global Clock Signal
input wire S_AXI_ACLK,
// Global Reset Signal. This Signal is Active LOW
input wire S_AXI_ARESETN,
// Write address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
// Write channel Protection type. This signal indicates the
// privilege and security level of the transaction, and whether
// the transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_AWPROT,
// Write address valid. This signal indicates that the master signaling
// valid write address and control information.
input wire S_AXI_AWVALID,
// Write address ready. This signal indicates that the slave is ready
// to accept an address and associated control signals.
output wire S_AXI_AWREADY,
// Write data (issued by master, acceped by Slave)
input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
// Write strobes. This signal indicates which byte lanes hold
// valid data. There is one write strobe bit for each eight
// bits of the write data bus.
input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
// Write valid. This signal indicates that valid write
// data and strobes are available.
input wire S_AXI_WVALID,
// Write ready. This signal indicates that the slave
// can accept the write data.
output wire S_AXI_WREADY,
// Write response. This signal indicates the status
// of the write transaction.
output wire [1 : 0] S_AXI_BRESP,
// Write response valid. This signal indicates that the channel
// is signaling a valid write response.
output wire S_AXI_BVALID,
// Response ready. This signal indicates that the master
// can accept a write response.
input wire S_AXI_BREADY,
// Read address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
// Protection type. This signal indicates the privilege
// and security level of the transaction, and whether the
// transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_ARPROT,
// Read address valid. This signal indicates that the channel
// is signaling valid read address and control information.
input wire S_AXI_ARVALID,
// Read address ready. This signal indicates that the slave is
// ready to accept an address and associated control signals.
output wire S_AXI_ARREADY,
// Read data (issued by slave)
output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
// Read response. This signal indicates the status of the
// read transfer.
output wire [1 : 0] S_AXI_RRESP,
// Read valid. This signal indicates that the channel is
// signaling the required read data.
output wire S_AXI_RVALID,
// Read ready. This signal indicates that the master can
// accept the read data and response information.
input wire S_AXI_RREADY
);
// AXI4LITE signals
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
reg axi_awready;
reg axi_wready;
reg [1 : 0] axi_bresp;
reg axi_bvalid;
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
reg axi_arready;
reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
reg [1 : 0] axi_rresp;
reg axi_rvalid;
// Example-specific design signals
// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
// ADDR_LSB is used for addressing 32/64 bit registers/memories
// ADDR_LSB = 2 for 32 bits (n downto 2)
// ADDR_LSB = 3 for 64 bits (n downto 3)
localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
localparam integer OPT_MEM_ADDR_BITS = 7;
//----------------------------------------------
//-- Signals for user logic register space example
//------------------------------------------------
//-- Number of Slave Registers 130
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg4;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg5;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg6;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg7;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg8;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg9;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg10;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg11;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg12;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg13;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg14;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg15;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg16;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg17;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg18;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg19;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg20;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg21;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg22;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg23;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg24;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg25;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg26;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg27;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg28;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg29;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg30;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg31;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg32;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg33;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg34;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg35;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg36;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg37;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg38;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg39;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg40;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg41;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg42;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg43;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg44;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg45;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg46;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg47;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg48;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg49;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg50;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg51;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg52;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg53;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg54;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg55;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg56;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg57;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg58;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg59;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg60;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg61;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg62;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg63;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg64;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg65;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg66;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg67;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg68;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg69;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg70;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg71;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg72;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg73;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg74;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg75;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg76;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg77;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg78;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg79;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg80;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg81;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg82;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg83;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg84;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg85;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg86;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg87;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg88;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg89;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg90;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg91;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg92;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg93;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg94;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg95;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg96;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg97;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg98;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg99;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg100;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg101;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg102;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg103;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg104;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg105;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg106;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg107;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg108;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg109;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg110;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg111;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg112;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg113;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg114;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg115;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg116;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg117;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg118;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg119;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg120;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg121;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg122;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg123;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg124;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg125;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg126;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg127;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg128;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg129;
wire slv_reg_rden;
wire slv_reg_wren;
reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out;
integer byte_index;
reg aw_en;
// I/O Connections assignments
assign S_AXI_AWREADY = axi_awready;
assign S_AXI_WREADY = axi_wready;
assign S_AXI_BRESP = axi_bresp;
assign S_AXI_BVALID = axi_bvalid;
assign S_AXI_ARREADY = axi_arready;
assign S_AXI_RDATA = axi_rdata;
assign S_AXI_RRESP = axi_rresp;
assign S_AXI_RVALID = axi_rvalid;
// Implement axi_awready generation
// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awready = slv_reg1[15:0]) begin
// full
slv_reg2[31:16] 1.3.6 打包
PROJECT MANAGER -> Edit Package IP – PS_PL_ADC_8B ->
-> File Groups -> Merge changes from File Groups Wizard
-> Customization Parameters -> Merge changes from File Groups Wizard
-> Review and Package -> Re-Package IP
1.4 创建一个block
1.4.1 zynq + hdmi
这里创建block按照 hdmi显示的过程进行。便于后续开发界面程序。
petalinux2018 zynq7 hdmi显示-CSDN博客
https://blog.csdn.net/qq_27158179/article/details/136232621
1.4.2 PS_PL_ADC_8B(ch1)
Diagram -> + -> PS_PL_ADC_8B_v1.0 -> OK
Run Connection Automation -> 勾选 All Automation -> OK
点击 PS_PL_ADC_8B_0 的 adc_clk -> 右键 -> Create Port ->
-> Port name: ad_clk_ch1
-> Direction: Output
-> Type: Clock
-> OK
点击 PS_PL_ADC_8B_0 的 adc_pd -> 右键 -> Create Port ->
-> Port name: ad_pd_ch1
-> Direction: output
-> Type: Other
-> OK
点击 PS_PL_ADC_8B_0 的 adc_data -> 右键 -> Create Port ->
-> Port name: ad_data_ch1
-> Direction: Input
-> Type: Other
-> OK
1.4.3PS_PL_DAC_8B(ch1)
Diagram -> + -> PS_PL_DAC_8B_v1_0 -> OK
Run Connection Automation -> 勾选 All Automation -> OK
点击 PS_PL_DAC_8B_0 的 dac_clk -> 右键 -> Create Port ->
-> Port name: da_clk_ch1
-> Direction: Output
-> Type: Clock
-> OK
点击 PS_PL_DAC_8B_0 的 dac_data -> 右键 -> Create Port ->
-> Port name: da_data_ch1
-> Direction: Input
-> Type: Data
-> OK
点击 PS_PL_DAC_8B_0 的 adc_pd -> 右键 -> Create Port ->
-> Port name: da_pd_ch1
-> Direction: output
-> Type: Other
-> OK
点击 PS_PL_DAC_8B_0 的 clk_50m -> 右键 -> Create Port ->
-> Port name: clk_50m
-> Direction: input
-> Type: Other
-> OK
1.4.4 ad和da的50Mhz时钟
连线
连接 端口 clk_50m 到 PS_PL_ADC_8B_0 的 clk_50m
连接 端口 clk_50m 到 PS_PL_DAC_8B_0 的 clk_50m
1.4.5 block diagram截图
只有zynq和hdmi:
只有zynq和adc dac：
zynq + hdmi + adc dac:
1.5 create HDL wrapper
source -> Design Source -> 右键 ZYNQ_CORE -> create HDL wrapper -> OK
1.6 引脚约束
添加约束文件，内容linux_sd_adda.xdc：
得到了 Sources -> Constrants -> constrs_1 -> linux_sd_adda.xdc
set_property PACKAGE_PIN H16 [get_ports clk_50m]
set_property IOSTANDARD LVCMOS33 [get_ports clk_50m]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_50m_IBUF]
set_property PACKAGE_PIN K17 [get_ports TMDS_0_clk_p]
set_property PACKAGE_PIN G19 [get_ports {TMDS_0_data_p[0]}]
set_property PACKAGE_PIN F19 [get_ports {TMDS_0_data_p[1]}]
set_property PACKAGE_PIN D19 [get_ports {TMDS_0_data_p[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {HDMI_OEN[0]}]
set_property PACKAGE_PIN M20 [get_ports {HDMI_OEN[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_0_tri_io[*]}]
set_property PACKAGE_PIN B19 [get_ports {GPIO_0_tri_io[7]}]
set_property PACKAGE_PIN J15 [get_ports {GPIO_0_tri_io[6]}]
set_property PACKAGE_PIN H17 [get_ports {GPIO_0_tri_io[5]}]
set_property PACKAGE_PIN B20 [get_ports {GPIO_0_tri_io[4]}]
set_property PACKAGE_PIN T19 [get_ports {GPIO_0_tri_io[3]}]
set_property PACKAGE_PIN R19 [get_ports {GPIO_0_tri_io[2]}]
set_property PACKAGE_PIN C20 [get_ports {GPIO_0_tri_io[1]}]
set_property PACKAGE_PIN G14 [get_ports {GPIO_0_tri_io[0]}]
set_property PACKAGE_PIN R18 [get_ports {da_data_ch1[0]}]
set_property PACKAGE_PIN T17 [get_ports {da_data_ch1[1]}]
set_property PACKAGE_PIN P20 [get_ports {da_data_ch1[2]}]
set_property PACKAGE_PIN N20 [get_ports {da_data_ch1[3]}]
set_property PACKAGE_PIN P18 [get_ports {da_data_ch1[4]}]
set_property PACKAGE_PIN N17 [get_ports {da_data_ch1[5]}]
set_property PACKAGE_PIN P19 [get_ports {da_data_ch1[6]}]
set_property PACKAGE_PIN N18 [get_ports {da_data_ch1[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {da_data_ch1[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {da_data_ch2[*]}]
set_property PACKAGE_PIN U12 [get_ports {ad_data_ch1[0]}]
set_property PACKAGE_PIN T12 [get_ports {ad_data_ch1[1]}]
set_property PACKAGE_PIN W13 [get_ports {ad_data_ch1[2]}]
set_property PACKAGE_PIN V12 [get_ports {ad_data_ch1[3]}]
set_property PACKAGE_PIN V13 [get_ports {ad_data_ch1[4]}]
set_property PACKAGE_PIN U13 [get_ports {ad_data_ch1[5]}]
set_property PACKAGE_PIN U15 [get_ports {ad_data_ch1[6]}]
set_property PACKAGE_PIN U14 [get_ports {ad_data_ch1[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ad_data_ch1[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ad_data_ch2[*]}]
set_property PACKAGE_PIN T10 [get_ports ad_clk_ch1]
set_property PACKAGE_PIN T20 [get_ports da_clk_ch1]
set_property PACKAGE_PIN T11 [get_ports ad_pd_ch1]
set_property IOSTANDARD LVCMOS33 [get_ports ad_clk_ch1]
set_property IOSTANDARD LVCMOS33 [get_ports da_clk_ch1]
set_property IOSTANDARD LVCMOS33 [get_ports ad_pd_ch1]
set_property IOSTANDARD LVCMOS33 [get_ports ad_clk_ch2]
set_property IOSTANDARD LVCMOS33 [get_ports da_clk_ch2]
set_property IOSTANDARD LVCMOS33 [get_ports ad_pd_ch2]
set_property PACKAGE_PIN R16 [get_ports {ad_data_ch2[7]}]
set_property PACKAGE_PIN R17 [get_ports {ad_data_ch2[6]}]
set_property PACKAGE_PIN V17 [get_ports {ad_data_ch2[5]}]
set_property PACKAGE_PIN V18 [get_ports {ad_data_c服务器托管网h2[4]}]
set_property PACKAGE_PIN T16 [get_ports {ad_data_ch2[3]}]
set_property PACKAGE_PIN U17 [get_ports {ad_data_ch2[2]}]
set_property PACKAGE_PIN T14 [get_ports {ad_data_ch2[1]}]
set_property PACKAGE_PIN T15 [get_ports {ad_data_ch2[0]}]
set_property PACKAGE_PIN R14 [get_ports ad_clk_ch2]
set_property PACKAGE_PIN P14 [get_ports ad_pd_ch2]
set_property PACKAGE_PIN J18 [get_ports {da_data_ch2[7]}]
set_property PACKAGE_PIN H18 [get_ports {da_data_ch2[6]}]
set_property PACKAGE_PIN G17 [get_ports {da_data_ch2[5]}]
set_property PACKAGE_PIN G18 [get_ports {da_data_ch2[4]}]
set_property PACKAGE_服务器托管网PIN K14 [get_ports {da_data_ch2[3]}]
set_property PACKAGE_PIN J14 [get_ports {da_data_ch2[2]}]
set_property PACKAGE_PIN H15 [get_ports {da_data_ch2[1]}]
set_property PACKAGE_PIN G15 [get_ports {da_data_ch2[0]}]
set_property PACKAGE_PIN J20 [get_ports da_clk_ch2]
set_property PACKAGE_PIN U20 [get_ports da_pd_ch1]
set_property PACKAGE_PIN H20 [get_ports da_pd_ch2]
set_property IOSTANDARD LVCMOS33 [get_ports da_pd_ch1]
set_property IOSTANDARD LVCMOS33 [get_ports da_pd_ch2]
set_property SLEW FAST [get_ports ad_clk_ch1]
set_property SLEW FAST [get_ports da_clk_ch1]
set_property SLEW FAST [get_ports {da_data_ch1[*]}]
set_property SLEW FAST [get_ports ad_clk_ch2]
set_property SLEW FAST [get_ports da_clk_ch2]
set_property SLEW FAST [get_ports {da_data_ch2[*]}]
1.7 编译
Run Synthesis
Run Implementation
Generate Bitstream
编译发现2块ADA106超出资源，暂时只用了1块ADA106
1.8 导出 HDF
Vivado -> File -> Export -> Export Hardware ->
-> Include bitstream -> OK
Vivado -> File -> Launch SDK -> OK
得到
linux_sd_adda/linux_sd_adda.sdk/hdmi_out_wrapper_hw_platform_0/system.hdf
下一篇：
petalinux_zynq7 C语言驱动DAC以及ADC模块之二https://blog.csdn.net/qq_27158179/article/details/136236138
服务器托管，北京服务器托管，服务器租用 http://www.fwqtg.net
目录 一、自学网络安全学习的误区和陷阱 二、学习网络安全的一些前期准备 三、网络安全学习路线 四、学习资料的推荐 想自学网络安全（黑客技术）首先你得了解什么是网络安全！什么是黑客！ 网络安全可以基于攻击和防御视角来分类，我们经常听到的 “红队”、“渗透测试” …
